1. Field of the Invention
The present invention relates generally to methods for forming trench fill layers within trenches within substrates employed in integrated circuit fabrication. More particularly, the present invention relates to methods for forming gap filling ozone assisted thermal chemical vapor deposited (CVD) silicon oxide trench fill layers within trenches within substrates employed in integrated circuit fabrication.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ trench isolation methods such as shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods to form trench isolation regions nominally co-planar with adjoining active semiconductor regions of semiconductor substrates. Such trench isolation methods typically employ a chemical mechanical polish (CMP) planarizing method to provide a nominally planarized surface to a trench isolation region formed from a trench fill dielectric layer formed within the trench. Trench isolation regions nominally co-planar with active semiconductor regions within semiconductor substrates are desirable since they optimize, when subsequently forming patterned layers upon those nominally co-planar trench isolation regions and active semiconductor regions, the limited depth of focus typically achievable with advanced photoexposure tooling.
When forming within advanced integrated circuits trench isolation regions within isolation trenches, it has become common to employ as trench fill dielectric layers gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods. Silicon oxide layers formed through such methods are desirable since such silicon oxide layers possess the inherently superior gap filling characteristics desirable for trenches of limited dimensions typically encountered in advanced integrated circuit fabrication.
While gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods are thus desirable as trench fill layers within trenches within advanced integrated circuit fabrication, methods through which are formed such gap filling silicon oxide layers are not entirely without problems. In particular, it is known in the art that gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods exhibit a surface sensitivity dependent upon the substrate layers upon which are formed those gap filling silicon oxide layers. In particular, when employing as substrate layers thermally grown silicon oxide layers which are typically employed as isolation trench liner layers within isolation trenches formed within semiconductor substrates, gap filling silicon oxide layers formed through ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods exhibit inhibited formation rates. Inhibited formation rates within isolation trenches within semiconductor substrates of gap filling silicon oxide trench fill layers formed through ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods are undesirable since there is then formed within those isolation trenches gap filling silicon oxide trench fill layers which are particularly susceptible to dishing when subsequently planarized through chemical mechanical polish (CMP) planarizing methods.
It is thus towards the goal of forming within advanced integrated circuits gap filling silicon oxide trench fill layers formed through ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods, while avoiding a surface sensitivity, that the present invention is generally directed.
Methods and materials through which silicon oxide layers may be formed with desirable properties within integrated circuits are known in the art of integrated circuit fabrication. For example, Wang et al, in U.S. Pat. No. 5,362,526 discloses several thermal chemical vapor deposition (CVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods for forming silicon oxide layers with gap filling properties over irregular surfaces within integrated circuits. The methods are characterized by comparatively high reactor chamber pressures. In addition, Hsia et al., in U.S. Pat. No. 5,393,708 discloses a method for forming a composite planarizing silicon oxide inter-metal dielectric (IMD) layer within an integrated circuit. The method employs a pair of silicon oxide layers formed through a plasma enhanced chemical vapor deposition (PECVD) method, a single silicon oxide layer formed through a thermal chemical vapor deposition (CVD) method and a single silicon oxide layer formed through a spin-on-glass (SOG) method.
Yet further, Ikeda, in U.S. Pat. No. 5,462,899 discloses an ozone assisted thermal chemical vapor deposition (CVD) method for forming a gap filling silicon oxide layer within an integrated circuit. The method employs a low ozone concentration within distribution piping through which is carried a tetra-ethyl-ortho-silicate (TEOS) silicon source material employed in forming the silicon oxide layer. Finally, Figura et al., in U.S. Pat. No. 5,472,904 disclose a method for simultaneously forming a silicon oxide narrow trench isolation region and a silicon oxide recessed oxide isolation (ROI) region within a semiconductor substrate. The method employs an oxidation barrier formed within a narrow trench within which is formed the silicon oxide narrow trench isolation region, but not within a wide trench within which is formed the silicon oxide recessed oxide isolation (ROI) region.
Desirable in the art are additional methods through which trenches within substrates employed within integrated circuit fabrication may be filled with gap filling silicon oxide trench fill layers formed through ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) methods, while avoiding a surface sensitivity when forming those gap filling silicon oxide trench fill layers. Particularly desirable are additional methods through which isolation trenches within semiconductor substrates employed within integrated circuit fabrication may be filled with gap filling silicon oxide trench fill dielectric layers formed through ozone assisted sub-atmospheric thermal chemical vapor deposition (SACVD) methods, while avoiding a surface sensitivity when forming those gap filling silicon oxide trench fill dielectric layers. It is towards these goals that the present invention is directed.